1. Field of the Invention
The invention relates to the technical field of DRAM (Dynamic Random Access Memory) access and, more particularly, to a control system and method for synchronous DRAM access.
2. Description of Related Art
With the progress of semiconductor technology, the access speed of DRAM has improved gradually. In past twenty years, the access speed of DRAM has increased from several MHz to several GHz, and the number of latency cycles of non-active bank memory access has increased gradually. For example, the number of latency cycles of non-active bank memory access in SDR is 3 to 5, and the numbers of latency cycles of non-active bank memory access in DDR-II and DDR-III are 12 to 25.
A computer system or an image processing system comprises various system bus masters. Each system bus master has a specific function, such as video decoding, video encoding, video display, audio signal decoding, audio signal play, DMA, etc. Since each system bus master executes the specific function, the system masters respectively access memory at inconsistent address range and command format at the same time. Thus, those DRAM commands will be accessed to different DRAM banks, pages and column address range. Since various system bus masters request the memory accesses that are for different data processing purpose or flow control of software program, it is difficult to find the same active page using in the previous memory access command and the following memory access command.
FIG. 1 is a schematic diagram of accessing different pages in typical DDR (Double data rate) DRAM read commands. It accesses twice at Bank-A of DRAM component, and the length of each access is burst-8. At the time T0, a memory controller outputs a precharge command into Bank-A of the DRAM. The memory controller outputs an active command into Bank-A of the DRAM at the time T3 after three clocks. These three clocks are determined based on tRP=3 in the specification of the DDR DRAM. The memory controller outputs a read command into Bank-A of the DRAM at the time T6 after three clocks. These three clocks are also determined based on tRCD=3 in the specification of the DDR DRAM. After three clocks (CL=3), at the time T9, the DRAM component outputs corresponding data (A1-A8) into its data bus. Since the second DRAM read command is proceeded to access different pages in Bank-A of the memory, the memory controller outputs a new precharge command into the DRAM at the time T11, and outputs an active command at the time T14. The timing of active commands in identical bank is determined by tRC=11 in the DDR SDRAM specification. As shown in FIG. 1, at the time T19, the memory outputs corresponding data (A9-A16) into its data bus (DDR DRAM DQ Signals), and it needs totally twenty-four clock cycles to complete two burst-8 DRAM read commands. It is obvious that this method of memory access is time-wasting and ineffective.
To overcome the aforementioned problem, FIG. 2 is a schematic diagram of prior accessing for DDR memory by interleaving algorithm. It separately proceeds to access for Bank-A and Bank-B of DRAM component, and the burst length of each access is burst-8. At the time T0, a memory controller outputs a precharge command into Bank-A of the DRAM component. At the time T2, a memory controller outputs a precharge command into Bank-B of the DRAM component. At the time T3, the memory controller outputs an active command into Bank-A of the DRAM component. At the time T5, the memory controller outputs an active command into Bank-B of the DRAM component, this active command and previous active command belong to different banks, so it is not limited to tRC=11 in the DDR DRAM specification. At the time T6, the memory controller outputs a read command into Bank-A of the DRAM component. At the time T9, Bank-A of the memory outputs read data (A1-A8) into its data bus. At the time T10, the memory controller outputs a read command into Bank-B of the DRAM component. After three clocks (CL=3), at the time T13, the memory outputs the read data (B1-B8) into its data bus, and it needs totally eighteen clock cycles to complete two burst-8 DRAM read commands. Although this method saves several clocks in comparison with the method in FIG. 1, memory controller needs to service a serial memory access requests from all system bus masters. Normally, there are no relationships between previous memory command and next memory command because they are from different system bus masters. The bank-interleave mechanism can not be applied to all DRAM commands of a serial memory access request and it is based on the possibility of permutation of memory access request. In the case, the memory controller can't provide maximal DRAM bandwidth to a computer system. For a 2-bank DRAM, the possibility of same DRAM bank and different page (row address) with previous DRAM command request and the next DRAM command request is around fifty percent. Therefore, there is a need for the above memory access control system to be improved.